Mostrando entradas con la etiqueta 3 Leonard Quintero. Mostrar todas las entradas
Mostrando entradas con la etiqueta 3 Leonard Quintero. Mostrar todas las entradas

martes, 16 de marzo de 2010

III-nitride semiconductor growth by MBE: Recent issues

III-nitride semiconductor growth by MBE: Recent issues

Auteur(s) / Author(s)
MORKOC Hadis ;
Résumé / Abstract
Semiconductor III-Nitrides, such as GaN, AIN, InN and their ternaries, have recently gained considerable attention after an uneven effort around the first half of the 1970s which paved the way to intense activity in the preceding decade. This is in part due to early obstacles achieving high quality layers, particularly those with p-type conductivity. With marketing of blue LEDs, the interest and consequently the effort grew to the point that CW lasers, high power amplifiers, and UV detectors have been added to the list of devices made in this material system. GaN and its allied semiconductors are grown with a variety of techniques. Generally, thick GaN layers are grown with hydride vapor phase epitaxy whereas the thin ones and heterojunctions formed by the above mentioned binaries and their ternaries are grown by organometallic vapor phase epitaxy and molecular beam epitaxy. OMVPE uses ammonia and metalorganics for group Vand III elements whereas MBE uses either ammonia or RF activated N2, and metal for group III elements. Among the above mentioned thin-film growth methods, only the issues pertaining to MBE will be reviewed in this paper.
Revue / Journal Title
Journal of materials science. Materials in electronics   ISSN 0957-4522 
Source / Source
2001, vol. 12, no12, pp. 677-695 [19 page(s) (article)]
Langue / Language
Anglais
Editeur / Publisher
Springer, Norwell, MA, ETATS-UNIS  (1990) (Revue)
Localisation / Location
INIST-CNRS, Cote INIST : 22352, 35400010346048.0010

Leonard Quintero C.I 18.424.427 (EES)

Epitaxial growth of III-V nitride semiconductors by metalorganic chemical vapor deposition

Epitaxial growth of III-V nitride semiconductors by metalorganic chemical vapor deposition

Auteur(s) / Author(s)
DUPUIS R. D. (1) ;
Affiliation(s) du ou des auteurs / Author(s) Affiliation(s)
(1) Microelectronics Research Center, The University of Texas at Austin, MER 1.606D-R9900, Austin, Texas 78712-1100, ETATS-UNIS
Résumé / Abstract
The III-V compound semiconductors are widely used throughout the world (as well as in space) for a wide variety of electronic and optoelectronic devices. Recently, a strong research and commercial interest has developed in the use of the III-V nitrides for visible (blue and green) light-emitting diodes and injection lasers and high-temperature electronics. The epitaxial growth of thin films and heterostructures of III-N was pioneered using the hydride vapor-phase epitaxial technique. However,in the past few years, the metalorganic chemical vapor deposition process has become the primary process for the growth of thin films of these compound semiconductors. This paper will discuss the growth of InAlGaN materials by metalorganic chemical vapor deposition.
Revue / Journal Title
Journal of crystal growth   ISSN 0022-0248   CODEN JCRGAE 
Source / Source
1997, vol. 178, no 1-2 (208 p.)  (99 ref.), pp. 56-73
Langue / Language
Anglais
Editeur / Publisher
Elsevier, Amsterdam, PAYS-BAS  (1967) (Revue)
Mots-clés anglais / English Keywords
Crystal growth methods ; Crystal growth from vapors ; MOCVD ; III-V semiconductors ; Instrumentation ; Precursor ; Substrates ; Operating mode ; Nitrides ; Crystal doping ; Epitaxy ; Selective area ; Injection laser ; Light emitting diodes ; Photodetectors ; Field effect transistors ; Semiconductor lasers ; Semiconductor devices ;
Mots-clés français / French Keywords
Méthode croissance cristalline ; Croissance cristalline en phase vapeur ; Méthode MOCVD ; Semiconducteur III-V ; Appareillage ; Précurseur ; Substrat ; Mode opératoire ; Nitrure ; Dopage cristal ; Epitaxie ; Aire sélective ; Laser injection ; Diode électroluminescente ; Photodétecteur ; Transistor effet champ ; Laser semiconducteur ; Dispositif semiconducteur ;
Mots-clés espagnols / Spanish Keywords
Método operatorio ; Laser inyección ;
Localisation / Location
INIST-CNRS, Cote INIST : 13507, 35400006738745.0050

Leonard Quintero C.I 18.424.427 (EES)

Nitride semiconductors free of electrostatic fields for efficient white light-emitting diodes

Nitride semiconductors free of electrostatic fields for efficient white light-emitting diodes

P. Waltereit, O. Brandt, A. Trampert, H. T. Grahn, J. Menniger, M. Ramsteiner, M. Reiche & K. H. Ploog
Paul-Drude-Institut für Festkörperelektronik, Hausvogteiplatz 5-7, D-10117 Berlin, Germany
Compact solid-state lamps based on light-emitting diodes (LEDs)1, 2 are of current technological interest as an alternative to conventional light bulbs. The brightest LEDs available so far emit red light and exhibit higher luminous efficiency than fluorescent lamps. If this luminous efficiency could be transferred to white LEDs, power consumption would be dramatically reduced, with great economic and ecological consequences. But the luminous efficiency of existing white LEDs is still very low, owing to the presence of electrostatic fields within the active layers3. These fields are generated by the spontaneous and piezoelectric polarization along the [0001] axis of hexagonal group-III nitrides—the commonly used materials for light generation4, 5, 6. Unfortunately, as this crystallographic orientation corresponds to the natural growth direction of these materials deposited on currently available substrates7. Here we demonstrate that the epitaxial growth of GaN/(Al,Ga)N on tetragonal LiAlO2 in a non-polar direction allows the fabrication of structures free of electrostatic fields, resulting in an improved quantum efficiency. We expect that this approach will pave the way towards highly efficient white LEDs.
Leonard Quintero C.I 18.424.427 (EES)

US Patent 6475277 - Group III-V nitride semiconductor growth method and vapor phase growth apparatus

US Patent 6475277 - Group III-V nitride semiconductor growth method and vapor phase growth apparatus

Abstract

A vapor phase growth apparatus 1 for growing a group III-V nitride semiconductor (GaN) comprises a reaction ampoule 3 having a container 11 disposed therein for containing a group III element and an inlet 7 for introducing nitrogen; excitation means 15 for plasma-exciting nitrogen introduced from the inlet 7; and heating means 13 for heating a seed crystal 10 disposed within the reaction ampoule 3 and the container 11; wherein, upon growing the group III-V nitride semiconductor on the seed crystal 10, nitrogen is introduced from the inlet 7, and no gas is let out from within the reaction ampoule 3.

Claims

1. A group III-V nitride semiconductor growth method for growing a group III-V nitride semiconductor on a seed crystal disposed within a reaction ampoule surrounded by a heater for heating said ampoule, said method comprising the steps of:

heating said reaction ampoule by said heater, said seed crystal being indirectly heated through said reaction ampoule;

plasma-exciting nitrogen continuously introduced into said reaction ampoule and evaporating a group III element disposed within said reaction ampoule; and

causing thus plasma-excited nitrogen and evaporated group III element to react with each other, so as to grow the III-V nitride semiconductor on said seed crystal,

wherein said step of growing the group III-V nitride semiconductor on said seed crystal includes a step of causing said reaction ampoule to maintain substantially a constant total pressure of about 10 Pa to about 4000 Pa therein.

2. A group III-V nitride semiconductor growth method according to claim 1, wherein positive and negative pulsed voltages are alternately applied between two electrodes, so as to plasma-excite said nitrogen between said electrodes.

3. A group III-V nitride semiconductor growth method for growing a group III-V nitride semiconductor on a seed crystal disposed within a reaction ampoule, said method comprising the steps of:

causing nitrogen continuously introduced into said reaction ampoule to react with hydrogen within said reaction ampoule upon plasma excitation, so as to generate a hydride of nitrogen, and causing said hydride of nitrogen and a group III element evaporated within said reaction ampoule to react with each other, so as to grow the group III-V nitride semiconductor on said seed crystal; and then
causing hydrogen generated upon growing said group III-V nitride semiconductor and nitrogen continuously introduced into said reaction ampoule to react with each other upon plasma excitation, so as to generate a hydride of nitrogen.

4. A group III-V nitride semiconductor growth method according to claim 3, wherein positive and negative pulsed voltages are alternately applied between two electrodes, so as to cause said nitrogen and said hydrogen upon plasma excitation between said electrodes.

5. A group III-V nitride semiconductor growth method according to claim 3, wherein said nitrogen is introduced into said reaction ampoule such that said reaction ampoule maintains substantially a constant total pressure therein.

6. A group III-V nitride semiconductor grouwth method for growing a group III-V nitride semiconductor on a seed crystal disposed within a closed reaction ampoule, said method compriing the stepd of:

causing a group III element disposed within said closed reaction ampoule and a halogen molecule of halide to react with each other, so as to generate a halide of said group III element, and causing said halide of group III element and plasma-excited nitrogen to react with each other, so as to grow the group III-V nitride semiconductor on said seed crystal; and then

causing the halogen molecule or halide generated when growing said group III-V nitride semiconductor and the group III element disposed within said closed reaction ampoule to react with wach other, so as to generate a halide of said group III element.

7. A group III-V nitride semiconductor growth method according to claim 6, wherein positive and negative pulsed voltages are alternately applied between two electrodes, so as to plasma-excite said nitrogen between said electrodes.

8. A group III-V nitride semiconductor growth method according to claim 6, wherein said nitrogen is introduced into said reaction ampoule such that said reaction ampoule maintains substantially a constant total pressure therein.

9. A group III-V nitride semiconductor growth method for growing a group III-V nitride semiconductor on a seed crystal disposed within a reaction ampoule, said method comprising the steps of:

causing nitrogen introduced into said reaction ampoule and hydrogen within said reaction ampoule to react with each other upon plasma excitation, so as to generate a hydride of nitrogen, and also causing a group III element disposed within said reaction ampoule and a halogen molecule or halide to react with each other, so as to generate a halide of said group III element, and causing said hydride of nitrogen and said halide of group III element to react with each other, so as to grow the group III-V nitride semiconductor on said seed crystal;
 
and then

causing said halogen molecule or halide generated upon growing said group III-V nitride semiconductor and the group III element disposed within said reaction ampoule to react with each other, so as to generate a halide of said group III element, and also causing hydrogen which is generated upon growing said group III-V nitride semiconductor and nitrogen to react with each other upon plasma excitation, so as to generate a hydride of nitrogen.

10. A group III-V nitride semiconductor growth method according to claim 9, wherein positive and negative pulsed voltages are alternately applied between two electrodes, so as to cause said nitrogen and said hydrogen to react with each other upon plasma excitation between said electrodes.

11. A group III-V nitride semiconductor growth method according to claim 9, wherein said nitrogen is introduced into said reaction ampoule such that said reaction ampoule maintains substantially a constant total pressure therein.

12. A vapor phase growth apparatus for growing a group III-V nitride semiconductor, said apparatus comprising:

a reaction ampoule having a container disposed therein for containing a group III element and an inlet for introducing nitrogen;

excitation means for plasma-exciting said nitrogen introduced from said inlet;

heating means surrounding said reaction ampoule for heating indirectly a seed crystal disposed within said reaction ampoule and said container; and

pressure means for maintaining at substantially a constant total pressure of about 10 Pa to about 4000 Pa therein,

wherein, upon growing the group III-V nitride semiconductor on said seed crystal, nitrogen is introduced from said inlet, and no gas is let out from within said reaction ampoule.

13. A vapor phase growth apparatus according to claim 12, wherein said excitation means has two electrodes, and a high-frequency power source for alternately applying positive and negative pulsed voltages between said

Leonard Quintero C.I 18.424.427 (EES)

METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATE

METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATE

Inventors:
Lai, Chih-ming (Pingtung County, TW)
Tsay, Jenq-dar (Kaohsiung City, TW)
Liu, Wen-yueh (Taipei City, TW)
Guo, Yih-der (Hsinchu City, TW)
Application Number: 12/581891
Publication Date: 02/18/2010
Filing Date: 10/20/2009
Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE (Hsinchu, TW)
Primary Class: 438/497
Other Classes: 257/E21.09, 438/798
International Classes: H01L21/20
Claims:
What is claimed is:

1. A method of forming a nitride semiconductor substrate, comprising: providing a substrate; forming a epitaxy layer on the substrate; forming a patterned mask layer on the epitaxy layer, wherein the patterned mask layer exposes a portion of the epitaxy layer; performing an oxidation process to completely oxidize the exposed epitaxy layer so as to form a plurality of dislocation blocking structure; removing the patterned mask layer; and forming a nitride semiconductor layer on the epitaxy layer having the dislocation blocking structures.

2. The method of claim 1, wherein the material of the substrate is selected from a group consisting of silicon, silicon carbide, aluminum oxide, sapphire, zinc oxide, magnesium oxide and a combination thereof.

3. The method of claim 2, the epitaxy layer includes a nitride epitaxy material layer.

4. The method of claim 3, the material of the nitride epitaxy material layer is selected from a group consisting of gallium nitride, indium nitride, aluminum nitride, indium gallium nitride, gallium aluminum nitride, indium aluminum nitride, aluminum indium gallium nitride and a combination thereof.

5. The method of claim 2, wherein the oxidation process comprises a step of using an electrolytic solution.

6. The method of claim 5, wherein the pH value of the electrolytic solution is between 3 and 10.

7. The method of claim 5, wherein the oxidation process further comprises a step of performing a high-energy light illuminating.

8. The method of claim 7, wherein the high-energy light illuminating process comprises a step of using an ultraviolet light.

Description:

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional application of and claims the priority benefit of patent application Ser. No. 11/562,422, filed on Nov. 22, 2006, which claims the priority benefit of Taiwan application serial no. 95132698, filed Sep. 5, 2006. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor substrate of group III-V, and more particularly to a method of manufacturing a nitride semiconductor substrate.
2. Description of Related Art
In the recent years, light emitting diodes (LED) and laser diodes (LD) have been prevailing in commercial use. For example, a mixture of blue and yellow phosphors made of gallium nitride (GaN) is capable of generating white light, which leads to a higher luminance and substantially lower power consumption than a conventional light bulb. In addition, the LED has a lifetime of more than tens of thousand hours, longer than that of conventional light bulbs.
The major components of red, green, blue, and ultraviolet LEDs obtained commercially are mostly GaN-series compound. However, since aluminum oxide substrate itself is different from GaN series in lattice constant, thermal expansion coefficients and chemical properties, the GaN layer growing on a heterogeneous substrate (e.g. a silicon substrate, a silicon carbide substrate, or an aluminum oxide substrate) may have linear defects and dislocations. The dislocations extend together with the increasing thickness of the growing GaN layer, resulting in the formation of threading dislocations. The foresaid defects would affect the laser performance of the ultraviolet LEDs and of the GaN-series compound and reduce their lifetime.
In order to reduce the threading dislocations, several substrate structures are then developed according to the prior art. FIG. 1 is a simplified sectional view illustrating a conventional nitride substrate of group III. Referring to FIG. 1, a GaN buffer layer 102 is disposed on a substrate 100, and several barrier structures 104 are disposed on the GaN buffer layer 102. Then, a semiconductor layer 106, i.e. a GaN epitaxy layer, is grown on the GaN buffer layer exposed among the barrier structures 104 and covers the barrier structures 104. In this substrate structure, the barrier structures are used to block some dislocations, so that a portion of the GaN epitaxy layer disposed on the barrier structures generates no threading dislocations. However, the barrier structures 104 are formed through at least once performance of photolithography and etching process, and vacuum apparatuses are also required to this manufacturing process; thus, the steps are more complicated and the cost is higher.
FIG. 2 is a simplified sectional view illustrating another conventional nitride substrate of group III. Referring to FIG. 2, a buffer layer 202 and a seed layer 204 are formed on the substrate 200. Trenches 206 passing through the buffer layer 202 and the seed layer 204 are then formed in the substrate 200. Namely, the buffer layer 202 and the seed layer 204 are patterned into strip or dot structures. A selective lateral overgrowth technique of a heterogeneous structure is called "pendeo-epitaxy" (PE) whereby the GaN epitaxy layer is simply suspended from and laterally grown on the sidewalls of the striped seed layer 204, such that the GaN epitaxy layer covers the striped seed layer 204 so as to block parts of the threading dislocations in a vertical direction. Similar to the barrier structures 104 illustrated in FIG. 1, the trenches 206 passing through the buffer layer 202 and the seed layer 204 are formed through at least once performance of photolithography and etching process, and vacuum apparatuses are also required for the manufacturing process; thus these steps are more complicated and the cost is higher.

SUMMARY OF THE INVENTION

The present invention provides a manufacturing method of a nitride semiconductor substrate. A substrate is provided and an epitaxy layer is formed on the substrate. Then, a patterned mask layer is formed on the epitaxy layer, wherein the patterned mask layer exposes a portion of the epitaxy layer. Next, an oxidation process is performed to completely oxidize the exposed epitaxy layer so as to form a plurality of dislocation blocking structures. The patterned mask layer is removed. Then, a nitride semiconductor layer is formed on the epitaxy layer having the dislocation blocking structures.
In order to the make aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures are described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a simplified sectional view illustrating a conventional nitride substrate of group III.
FIG. 2 is a simplified sectional view illustrating another conventional nitride substrate of group III.
FIGS. 3A to 3C depict a manufacturing method of a nitride semiconductor substrate according to one embodiment of the present invention.
FIGS. 4A to 4C depict a manufacturing method of a nitride semiconductor substrate according to another embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
FIGS. 3A to 3C depict a manufacturing method of a nitride semiconductor substrate according to one preferred embodiment of the present invention.
Firstly, refer to FIG. 3A, a substrate 300 is provided. Next, an epitaxy layer 302 is formed on the substrate 300. Next, a patterned mask layer 304 is formed on the epitaxy layer 302. The patterned mask layer 304 exposes a portion of the epitaxy layer 302. The patterned mask layer 304 is, for example, a photoresist layer. Then, refer to FIG. 3B, an oxidation process 306 is performed by using the patterned mask layer 304 as a mask to completely oxidize the exposed epitaxy layer 302 to form a plurality of blocking structures 308, namely the dislocation blocking structures.
It should be noted that in one embodiment of the present invention, when the material of the substrate 300 is selected from a group consisting of silicon, silicon carbide, aluminum oxide, sapphire, zinc oxide, magnesium oxide and a combination thereof, the epitaxy layer 302 formed on the substrate 300 is, for example, a nitride epitaxy material layer. The foresaid nitride epitaxy material layer is selected from one group consisting of gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), indium gallium nitride, aluminum gallium nitride, indium aluminum nitride, aluminum indium gallium nitride and a combination thereof. When the materials of substrate 300 and epitaxy layer 302 are as mentioned above, the oxidation process 306 is performed. In the oxidation process 306, the substrate 300 comprising epitaxy layer 302 and patterned mask layer 304 thereon is, under the room temperature of 0˜80° C., immersed in an electrolytic solution to proceed the oxidation so as to completely oxidize the exposed epitaxy layer; and in this way, the blocking structures 308 are formed. In this process, the pH value of the electrolytic solution is between 3 and 10. The way to prepare this electrolytic solution is to dissolve nitrilotriacetic acid in the potassium hydroxide solution. Besides, at the time the oxidation process 308 is performed, the process of high-energy light illuminating is proceeded. Namely, using the high-energy light, e.g. the ultraviolet light, accelerates the oxidation in the electrolytic solution. The wavelength of the foresaid high-energy light is shorter than that of the light which can penetrate the epitaxy layer 302.
In another embodiment, when the material of the substrate 300 is selected from a group consisting of gallium arsenide, gallium phosphide, gallium arsenide phosphide, gallium arsenide aluminum, other arsenide and phosphide and a combination thereof, the epitaxy layer 302 is, for example, an arsenide epitaxy material containing aluminum. The foresaid arsenide epitaxy material containing aluminum is, for example, an arsenide (AlXGa(1-X)As) epitaxy material containing aluminum and gallium. Wherein, the X is larger than 0.8. That is, in the arsenide epitaxy material containing aluminum and galliumthe, the ratio between the aluminum atoms and the total number of aluminum atoms and the gallium atoms is larger than 0.8. When the materials of substrate 300 and epitaxy layer 302 are as mentioned above, the oxidation process 306 is performed. In the oxidation process 306, the substrate 300 comprising epitaxy layer 302 and patterned mask layer 304 thereon is, under the high temperature of 200˜600° C., placed in the condition of water vapor to proceed a wet oxidation step.
In the foresaid embodiment, the oxidation process 306 is performed to completely oxidize the exposed epitaxy layer so as to form the blocking structures 308. The material of the blocking structures 308 is selected from a group consisting of aluminum oxide, gallium oxide and a combination thereof.
Referring to FIG. 3C, the patterned mask layer 308 is removed. Next, a nitride semiconductor layer 310 is formed over the substrate 300. The way to form the nitride semiconductor layer 310 includes an epitaxial process, such as an organic-metal vapor epitaxy method or a metal-organic chemical vapor epitaxy method.
In the performance of the epitaxial process, due to the oxide porous characteristic of the blocking structures 308, the nitride semiconductor layer 310, such as gallium nitride, indium nitride, aluminum nitride, indium gallium nitride, aluminum gallium nitride, indium aluminum nitride, and aluminum indium gallium nitride semiconductor layer, does not form epitaxy on the blocking structures 308, but forms epitaxy on the surface of epitaxy layer 302, which fills the space between the blocking structures 308. The nitride semiconductor layer 310 grows in a lateral direction so as to block parts of the threading dislocations in the nitride semiconductor layer. Therefore, the threading dislocation density of the grown nitride semiconductor layer is reduced.
FIGS. 4A to 4C depict a manufacturing method of a nitride semiconductor substrate according to another preferred embodiment of the present invention.
Firstly, refer to FIG. 4A, a substrate 400 is provided. Next, an epitaxy layer 402 is formed on the substrate 400. Next, a patterned mask layer 404 is formed on the epitaxy layer 402. The patterned mask layer 404 exposes a portion of the epitaxy layer 402. The patterned mask layer 404 is, for example, a photoresist layer. Then, refer to FIG. 4B, an oxidation process 406 is performed by using the patterned mask layer 404 as a mask to partly oxidize the exposed epitaxy layer 402 so as to form a plurality of blocking structures 408, namely the dislocation blocking structures.
It should be noted that in this embodiment, the blocking structures 408 are disposed in the epitaxy layer 402. Referring to the embodiment of 3A to 3C, the blocking structures 308 are disposed on the substrate 300, and at the same time, the epitaxy layer 302 is disposed on the substrate 300 and fills the space between blocking structures 308. Different from the blocking structures 308 illustrated in the embodiment of 3A to 3C, the blocking structures 408 in this present embodiment are disposed in the epitaxy layer 402, and the bottom of the blocking structure 408 is not directly contacted with the substrate 400.
Moreover, since the material of substrate 400 and epitaxy layer 402 in this embodiment is the same with the material of substrate 300 and epitaxy layer 302 in the previous embodiment, the detailed description of material will not be explained here. Similarly, the method to form the blocking structure 408 in the epitaxy layer 402 is the same with the method to form the blocking structure 308 in the previous embodiment; the detailed description is omitted here. Further, since the material of blocking structure 408, namely the oxide material, is the same with the material of blocking structure 308, no detailed descriptions are required here.
Then, refer to FIG. 4C, the patterned mask layer 408 is removed. Afterward, a nitride semiconductor layer 410 is formed over the substrate 400. The method to form this nitride semiconductor layer 410 is an epitaxial process, such as an organic-metal vapor epitaxy method or a metal-organic chemical vapor epitaxy method. In the performance of epitaxial process, due to the oxide porous characteristic of the blocking structure 408, the nitride semiconductor layer 410, such as nitride semiconductor layer of the gallium nitride, indium nitride, aluminum nitride, indium gallium nitride, aluminum gallium nitride, indium aluminum nitride, and aluminum indium gallium, does not form epitaxy on the blocking structure 408, but forms epitaxy on the surface of epitaxy layer 402. The nitride semiconductor layer 410 grows in a lateral direction so as to block parts of the threading dislocations in the nitride semiconductor layer. Therefore, the threading dislocation density of the grown nitride semiconductor layer is reduced.
Besides, the present invention uses the technique of oxidation process to directly oxidize the epitaxy layer on the substrate so as to form the blocking structure. Compared to the prior art of applied etching process to form blocking structure, this present invention can reduce the manufacturing cost.Although the present invention has been disclosed above by the preferred embodiments, they are not intended to limit the present invention. Anybody skilled in the art can make some modifications and alteration without departing from the spirit and scope of the present invention. Therefore, the protecting range of the present invention falls in the appended claims.
Leonard Quintero C.I 18.424.427 (EES)

GROWTH AND STRUCTURE OF POLYMORPHOUS SILICON A MATERIAL OBTAINED BY THE INCORPORATION OF SILICON NANOPARTICLES IN AN AMORPHOUS MATRIX-APPLICATION TO THIN FILM TRANSISTORS

GROWTH AND STRUCTURE OF POLYMORPHOUS SILICON A MATERIAL OBTAINED BY THE INCORPORATION OF SILICON NANOPARTICLES IN AN AMORPHOUS MATRIX-APPLICATION TO THIN FILM TRANSISTORS
Autor: FONTCUBERTA MORRAL ANNA.
Año: 2001.
Universidad: BARCELONA.
Centro de lectura: FÍSICA.
Centro de realización: UNVIERSITAT DE BARCELONA.
Resumen: El trabajo presentado en este manuscrito de tesis está destinado a la comprensión de un nuevo material desarrollado en el Laboratorio de Física de Interficies y Capas Delgadas (Ecole Polytechnique, Palaiseau): el silicio polimorfo (pm-Si:H). El desarrollo de este material está ligado al estudio de la formación de polvo en los plasmas de silano. Se considera polvo a partículas que pueden llegar a las varias micras de diámetro, pero los precursores de las cuales son entidades de pocos nanómetros. Es lo que llamamos nano-partículas. El silicio polimorfo se deposita en condiciones de plasma cercanas a la formación de polvo, lo cual debería de resultar en la incorporación de nano-partículas en el material. Des de 1998 toda una serie de experiencias muestran que el pm-Si:H tiene propiedades eléctricas mejores que el silicio amorfo estándar (a-Si:H). Además, se realizaron dispositivos fotovoltaicos con pm-Si:H, dando lulgar a células solares estables con la exposición al sol. Son precisamente estas cualidades las que motivaron todo este estudio sobre su estructura y condiciones de elaboración. Este trabajo ha sido abordado des de tres puntos de vista diferentes: el plasma, el crecimiento y su estructura. La naturaleza particular de este material ha necesitado el desarrollo de varias técnicas especiales. Por un lado, los estudios de la Cavidad Láser Resonante permiteiron de medir concentraciones de nano-partículas del orden de 10-10 cm-3, en condiciones de obtención del pm-Si:H. Por otro lado, los estudios in situ realizados por Elipsometría Espectroscópica (SE) mostraron un crecimiento homogéneo del material. La interpretación de la función dieléctrica del material obtenida por (SE) necesitó el desarrollo del modelo de Tetraedro. Esto permitió de avanzar en la comprensión de la estructura de este material. Vimos como el pm-Si:H se trata de un material con mucho hidrógeno (15-25%), pero al mismo tiempo con una fracción de huecos muy baja (material denso). Para determinar, los estudios realizados en Microscopía Elctrónica a Transmisión de alta resolución indicaron la presencia de nano-cristales en una matriz amorfa. Análisis por Transformada de Fourier muestran que se trata de una matriz con un grado de ordenamiento más alto que el a-Si:H estándar, lo que podría explicar que las propiedades eléctricas del pm-Si:H sean mejores. Al final del manuscrito se presenta la aplicación de una serie de pm-Si:H como capa activa de Transistores en Capa Delgada. El resultado concuerda con los estudios estructurales: los transistores con mejroes características coinciden con el material que presenta un mayor orden estructural. La obtención de movilidades de hasta 0,8 cm2/Vs es un excelente resultado y abre más perspectivas para la aplicación de este material en la industria electrónica de gran superficie.
Leonard Quintero C.I 18.424.427 (EES)

Crecimiento y caracterización de nitruros de cobre

Crecimiento y caracterización de nitruros de cobre

Nuria Gordillo García
Centro de Microanálisis de Materiales (CMAM)

En los últimos años ha aumentado notablemente el interés por los nitruros metálicos de transición (NMT) debido al gran potencial que presentan para la fabricación de ciertos dispositivos en aplicaciones eléctricas, ópticas y magnéticas. Sin embargo, una de las propiedades más notoria e interesante de este tipo de materiales, sea tal vez, la extrema dependencia de sus propiedades físicas en función de la composición química, en particular, con el contenido real de nitrógeno. [1, 2, 3]. Tradicionalmente, la mayor parte de las investigaciones han estado orientadas al estudio de nitruros termodinámicamente estables: GaN, InN [4, 5]. Actualmente, se esta prestando más atención a los nitruros metaestables, como el Cu3N o el FeN que a una determinada temperatura, relativamente baja, se descomponen en N2 y Cu o Fe, respectivamente. En particular, la descomposición del Cu3N mediante irradiación con láser, electrones o iones genera líneas microscópicas y nano partículas metálicas [6, 7, 8, 9] haciendo que este material sea muy atractivo para la industria electrónica.
A pesar de su potencial en distintos tipos de aplicaciones, la implementación industrial de dispositivos basados en Cu3N no se ha hecho realidad. Esto se debe fundamentalmente a la dispersión de datos sobre sus propiedades físicas presentes en la literatura. Por ejemplo, encontramos que el gap óptico varía de 1.2 a 1.9 eV. (38% de variación) [7,8,10,11] y la resistencia eléctrica medida oscila desde 2.6x10 5 a 1000W∙cm, es decir, de un comportamiento cuasi metálico al de un semiconductor intrínseco [7,8]. Esta dispersión de datos está relacionada con la ausencia de caracterización del contenido real de nitrógeno en las muestras. En este trabajo se presenta un estudio sistemático realizado en películas delgadas de nitruro de cobre depositadas mediante pulverización catódica (DCsputtering). En una primera parte se estudia la dependencia de la composición química de las muestras así como de sus propiedades estructurales y ópticas en función de los parámetros de crecimiento: presión parcial de nitrógeno (PN2) y voltaje de cátodo (DCbias) [12]. La caracterización de las muestras, mediante técnicas de análisis con haces de iones (IBA), dan como resultado una composición química con un contenido de nitrógeno entre 26 at. %33 at. % en función del PN2 y DC aplicados. Medidas de difracción de rayosX (XRD) muestran que la mayor parte de las muestras son poli cristalinas con una dirección preferencial  á 100ñ . Las medidas ópticas revelan que las muestras con una composición cercana a Cu3N se comportan como semiconductores intrínsecos de gap directo, mientras que las muestras con concentraciones mayores de nitrógeno presentan una contribución adicional de portadores libres. La dependencia de los parámetros característicos de la contribución de portadores libres será discutida en función del contenido nitrógeno. Posteriormente se estudiará la estabilidad térmica de este tipo de materiales a temperaturas inferiores a la de su descomposición, observándose que a temperaturas tan bajas como 100ºC se produce una segregación de fases relacionada con la migración del nitrógeno.

Leonard Quintero C.I 18.424.427 (EES)

US Patent 7023025 - Crystal growth method of nitride semiconductor

US Patent 7023025 - Crystal growth method of nitride semiconductor


TECHNICALFIELD

This Nonprovisional application claims priority under 35 U.S.C. § 119(a) on Patent Application No. 10-2003-0005948 filed in KOREA on Jan. 29, 2003, the entire contents of which are hereby incorporated by reference.

The present invention relates to a method of manufacturing a nitride semiconductor, and, more particularly, a crystal growth method of a nitride semiconductor wherein a nitride semiconductor is grown on a nitride buffer layer including aluminum so that it is possible to improve electrical and crystalline characteristics.
BACKGROUND OF THE INVENTION

Photoelectric elements and electric elements using Group III-V nitride semiconductors are developed actively. Luminescence diode and a laser diode with ultraviolet range or visible range are applied to many fields and their application will be extended more widely in the near future.

It is difficult to grow a nitride semiconductor film and elements of a good quality since nitride substrate of a mono-crystal having a good character is hard to make.

So, conventionally, the nitrides were grown on double-substrates of such as GaAs, ZnO, Sapphire, SiC, etc. Among them, nitride films grown on Sapphire substrate and SiC have specially a good quality enough to be used widely for manufacturing elements.

SiC has a good electric conductivity but very expensive so that most elements are using the nitrides grown on substrate of Sapphire.

Improving the characteristics of the films of the nitride semiconductors is due to the development of growth technology of the nitrides.


In order to grow a nitride film on upper substrate of Sapphire, the Sapphire substrate has to be treated at a high temperature, and then buffer layer is made on it at a low temperature (450˜600° C.). After that, the nitride film is grown on the buffer layer at a high temperature.

During this process, buffer layer growth is important.

semiconductors grown as a conventional method of crystal growth, which comprise the process of growing the buffer layer of the bivalent nitride (11) on the upper substrate of sapphire (10) and the process of growing the layers of the nitride semiconductor (12) on said Group-2 nitride buffer layers.

The necessity of the buffer layer is due to the difference between thermal expansion and the lattice constant of a sapphire substrate and the nitride which grows on the sapphire substrate (10). Namely, to overcome the differences of the thermal expansion and the lattice constant between the nitrides and the sapphire substrate (10), the nitride semiconductor (12) is grown after the layer of bivalent nitride (11) which is selected from GaN, AlN, InN and SiNx or the compounds thereof, is grown on a sapphire substrate (10), as shown FIG. 1.

The nitride film which was grown like the above is not single crystal but polymer or poly crystal so that it can be a seed layer to be able to grow a layer of the nitride compound semiconductor

Using the conventional single buffer layers of such like said GaN, AIN, InN, SiNx, etc., makes the nitride film with an improved characteristics in crystallographical view, but still has lots of problem to overcome the different physical characteristics between sapphire and GaN.

Therefore, in order to get a nitride semiconductor layer with the improved crystalline characteristics a new growth method or development of a new buffer layer is necessary, and this is the core for the improved function of the final product, i.e., elements.

In order to solve the said problems, the present invention provides a method of manufacturing of nitride semiconductor layer with improved electrical and crystalline characteristics by growth the nitride semiconductors on upper substrate of the nitride buffer layer which includes the aluminum.

The present invention provides a method of manufacturing of nitride semiconductor layer comprising: a first step of growing a buffer layer including aluminum on the top of sapphire substrate; a second step of growing bivalent nitride buffer layers on the top of said nitride buffer layers including aluminum; and a third step of growing a nitride semiconductor on the top of said bivalent nitride buffer layers.

SUMMARY OF THE INVENTION


An object of the present invention is to provide a nitride semiconductor comprising a metal oxide layer, said metal, formed on said metal oxide layer, a second nitride buffer layer formed on said first nitride buffer layer, and a nitride layer formed on said nitride buffer layers.

Another object of the present invention is to provide the nitride semiconductor wherein said metal oxide layer is a sapphire substrate and said metal is aluminum.

Further object of the present invention is to provide the nitride semiconductor, wherein said first and second nitride buffer layers include Indium.

According to an aspect of the present invention, the nitride semiconductor, wherein said second nitride buffer layer is a bivalent nitride layer.

According to another aspect of the present invention, the nitride semiconductor, wherein said third nitride buffer layer which does not include said metal, is formed between said first nitride buffer layer and said second nitride buffer.

Leonard Quintero C.I 18.424.427 (EES)

Low Temperature Nitride Semiconductor Growth

Low Temperature Nitride Semiconductor Growth

October
Macquarie University hosts the premier nitride semiconductor growth laboratory in Australia. Work on the nitrides began here in the early 1980s. Our research has concentrated on the low temperature, low substrate damage growth of aluminium nitride, gallium nitride, indium nitride and their alloys. A state-of-the-art low temperature chemical vapor deposition (CVD) unit has been built for the growth of these semiconductors. The system includes an ArF excimer laser used to crack precursor gases using photolysis (laser induced CVD) and a remote microwave plasma source to supply precursor radicals, especially atomic nitrogen (remote plasma enhanced CVD). Indium nitride is also grown at Macquarie using a radio-frequency reactive sputtering unit, despite the simplicity of this method it still provides the best quality InN.
Why nitride semiconductors? Since the early 1990s the group III nitride semiconductor gallium nitride, sometimes alloyed with indium nitride and aluminum nitride, has been used to fabricate very bright blue, violet, blue-green and white light emitting diodes (LEDs). The white LEDs will replace standard light bulbs over the next few years. Laser diodes are also being developed for high density optical storage – the next generation of DVDs. In addition solar blind UV detectors and high speed high power transistor devices (HEMT and HBT) have also been developed. In less than a decade nitride semiconductors have become some of the hottest materials around.
Why low temperatures? At present best quality gallium nitride is grown above 1000o C, by a method called MOCVD, on expensive sapphire or SiC substrates. Growth at lower temperatures would allow less expensive substrate materials, such as glass, to be used. It is also important that the atomic spacing of the substrate and the nitride films should match as closely as possible to inhibit strain in the film i.e. a close lattice match is required. Sapphire and gallium nitride do not have a close lattice match, but some temperature sensitive materials, such as ZnO, have only a very small lattice mismatch with gallium nitride. By growing at lower temperatures we hope to be able to use cheaper substrates, and substrates that are closely lattice matched to GaN.
Indium Nitride Emerges. Over twenty years ago the world's purest indium nitride was grown at Macquarie University by Trevor Tansley and Cathey Foley. This record has never been equaled. Now after more than two decades in the wilderness, international interest in indium nitride is being fueled by the potential to create higher mobility (faster) high power nitride based transistor devices. The old apparatus used to create the highest mobility (fastest) indium nitride ever grown is still in existence at Macquarie University, and has recently been upgraded to attempt another Macquarie led assault on the old record. The hope here is to understand the film growth parameters to the point where high mobility material can be routinely grown at Macquarie. If this can be achieved then the University will begin to supply this material to research groups around the world on a commercial basis.
Some of the group history and achievements:
Highest mobility nitride film ever grown (1984)
Highest purity indium nitride ever grown (1984)
High quality aluminium nitride insulating films grown by LICVD (1993)
Gallium nitride with 200 cm2·V-1·s-1 carrier mobility grown at 650o C using RPE-LICVD (1996)
Highest mobility n-type gallium nitride film ever grown on glass (2000)
Ultra-high resistivity aluminium nitride grown at room temperature (2001)
Currently, we are extending our studies to include device applications of low temperature grown GaN, in the direction of heteropolar devices such as light emitting diodes grown on glass and heterojunction bipolar transistors.
Recent Funding:
We graciously acknowledge the funding recently received by us from NICOP in partnership with the U.S. Office of Naval Research. In particular we acknowledge Dr Colin Wood and Dr Jaime Freitas Jr. for their roles in this support. These funds have been instrumental in allowing the update of our low temperature metalorganic CVD growth system, and has allowed us to greatly forward our understanding of low temperature growth processes. The U.S. Office of Naval Research also provides a useful on-line semiconductor based facility - the U.S. National Compound Semiconductor Roadmap.
Funding from the Australian Institute of Nuclear Science and Engineering (AINSE) has allowed us access to a Cameca 5f SIMS system for the analysis of the composition of our nitride films. Through AINSE we also have access to a DLTS facility that allows us to probe the electronic defect structure of our films.

Not least of all in this list we must thank Macquarie University, the Division of ICS and the Physics Department for their continuing support. Dr K. S. A. Butcher is particularly thankful for the support of a Macquarie University Research Fellowship (MURF).

Leonard Quintero C.I 18.424.427 (EES)